View HFA1115_2758033.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 tm HFA1115 225mhz, low power, output limiting, closed loop buffer amplifier the HFA1115 is a high speed closed loop buffer featuring both user programmable gain and output limiting. manufactured on intersil?s proprietary complementary bipolar uhf-1 process, the HFA1115 also offers a wide -3db bandwidth of 225mhz, very fast slew rate, excellent gain flatness and high output current. this buffer is the ideal choice for high frequency applications requiring output limiting, especially those needing ultra fast overload recovery times. the limiting function allows the designer to set the maximum positive and negative output levels, thereby protecting later stages from damage or input saturation. the HFA1115 also allows for voltage gains of +2, +1, and -1, without the use of external resistors. gain selection is accomplished via connections to the inputs, as described in the ?application information? text. the result is a more flexible product, fewer part types in inventory, and more efficient use of board space. compatibility with existing op amp pinouts provides flexibility to upgrade low gain amplifiers, while decreasing component count. unlike most buffers, the standard pinout provides an upgrade path, should a higher closed loop gain be needed at a future date. for military product, refer to the HFA1115/883 data sheet. pinout HFA1115 (pdip, soic) top view features ? user programmable output voltage limiting ? high input impedance . . . . . . . . . . . . . . . . . . . . . . . 1m ? ? differential gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.02% ? differential phase. . . . . . . . . . . . . . . . . . . . . 0.03 degrees ? wide -3db bandwidth (a v = +2) . . . . . . . . . . . . . 225mhz ? very fast slew rate (a v = -1) . . . . . . . . . . . . . . 1135v/ s ? low supply current . . . . . . . . . . . . . . . . . . . . . . . . 7.1ma ? high output current . . . . . . . . . . . . . . . . . . . . . . . . . 60ma ? excellent gain accuracy . . . . . . . . . . . . . . . . . . . 0.99v/v ? user programmable for closed-loop gains of +1, -1 or +2 without use of external resistors ? fast overdrive recovery . . . . . . . . . . . . . . . . . . . . . <1ns ? standard operational amplifier pinout applications ? flash a/d drivers ? video cable drivers ? high resolution monitors ? professional video processing ? medical imaging ? video digitizing boards/systems ? battery powered communications pin descriptions name pin number description nc 1 no connection -in 2 inverting input +in 3 non-inverting input v- 4 negative supply v l 5 lower output limit out 6 output v+ 7 positive supply v h 8 upper output limit nc -in +in v- 1 2 3 4 8 7 6 5 v h v+ out v l + _ 350 350 ordering information part number (brand) temp. range ( o c) package pkg. no. HFA1115ip -40 to 85 8 ld pdip e8.3 HFA1115ib (h1115i) -40 to 85 8 ld soic m8.15 hfa11xxeval high speed op amp dip evaluation board data sheets september 1998 fn3606.4 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved
2 absolute maximum ratings thermal information voltage between v+ and v-. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11v dc input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v supply output current (note 2) . . . . . . . . . . . . . . . . short circuit protected esd rating human body model (per mil-std-883 method 3015.7) . . . .600v operating conditions temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to 85 o c supply voltage range (typical) . . . . . . . . . . . . . . . . . . . 5v to 10v thermal resistance (typical, note 1) ja ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 maximum junction temperature (die). . . . . . . . . . . . . . . . . . . . 175 o c maximum junction temperature (plastic packages) . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . 300 o c (soic - lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ja is measured with the component mounted on an evaluation pc board in free air. 2. output is protected for short circuits to ground. brief short circuits to ground will not degrade reliability, however, conti nuous (100% duty cycle) output current should not exceed 30ma for maximum reliability. electrical specifications v supply = 5v, a v = +1, r l = 100 ? , unless otherwise specified parameter test conditions (note 3) test level temp. ( o c) min typ max units input characteristics output offset voltage a 25 - 2 10 mv afull-315mv average output offset voltage drift b full - 22 70 v/ o c common-mode rejection ratio ? v cm = 1.8v a 25 42 45 - db ? v cm = 1.8v a 85 40 44 - db ? v cm = 1.2v a -40 40 45 - db power supply rejection ratio ? v ps = 1.8v a 25 45 49 - db ? v ps = 1.8v a 85 43 48 - db ? v ps = 1.2v a -40 43 48 - db non-inverting input bias current a 25 - 1 15 a afull-325 a non-inverting input bias current drift b full - 30 80 na/ o c non-inverting input bias current power supply sensitivity ? v ps = 1.25v a 25 - 0.5 1 a/v afull--3 a/v non-inverting input resistance ? v cm = 1.8v a 25 0.8 1.1 - m ? ? v cm = 1.8v a 85 0.5 1.4 - m ? ? v cm = 1.2v a -40 0.5 1.3 - m ? inverting input resistance c 25 280 350 420 ? input capacitance c 25 - 1.6 - pf input voltage common mode range (implied by v io cmrr and +r in tests) a 25, 85 1.8 2.4 - v a-40 1.2 1.7 - v input noise voltage density (note 4) f = 100khz b 25 - 7 - nv/ hz non-inverting input noise current density (note 4) f = 100khz b 25 - 3.6 - pa/ hz HFA1115
3 transfer characteristics gain a v = -1 a 25 -0.98 -0.996 -1.02 v/v a full -0.975 -1.000 -1.025 v/v a v = +1 a 25 0.98 0.992 1.02 v/v a full 0.975 0.993 1.025 v/v a v = +2 a 25 1.96 1.988 2.04 v/v a full 1.95 1.990 2.05 v/v ac characteristics -3db bandwidth (v out = 0.2v p-p , note 4) a v = -1 b 25 - 225 - mhz a v = +1, +r s = 620 ? b25-200-mhz a v = +2 b 25 - 225 - mhz full power bandwidth (v out = 5v p-p at a v = +2/-1, 4v p-p at a v = +1, note 4) a v = -1 b 25 - 157 - mhz a v = +1, +r s = 620 ? b25-140-mhz a v = +2 b 25 - 125 - mhz gain flatness (to 25mhz, v out = 0.2v p-p , note 4) a v = +1, +r s = 620 ? b25- 0.1 - db a v = +2 b 25 - 0.04 - db gain flatness (to 50mhz, v out = 0.2v p-p , note 4) a v = +1, +r s = 620 ? b25- 0.25 - db a v = +2 b 25 - 0.1 - db output characteristics output voltage swing (note 4) a v = -1, r l = 100 ? a25 3.0 3.2 - v afull 2.8 3.0 - v output current (note 4) a v = -1, r l = 50 ? a 25, 85 50 55 - ma a -402842-ma output short circuit current b 25 - 90 - ma output resistance (note 4) dc, a v = +2 b 25 - 0.07 - ? second harmonic distortion (a v = +2, v out = 2v p-p ) 10mhz b 25 - -50 - dbc 20mhz b 25 - -45 - dbc third harmonic distortion (a v = +2, v out = 2v p-p ) 10mhz b 25 - -50 - dbc 20mhz b 25 - -45 - dbc transient response a v = +2, unless otherwise specified rise and fall times (v out = 0.5v p-p , note 4) rise time b 25 - 1.7 - ns fall time b 25 - 1.9 - ns overshoot (v out = 0.5v p-p , v in t rise = 2.5ns) +os b 25 - 0 - % -os b 25 - 0 - % slew rate (v out = 5v p-p , a v = -1) +sr b 25 - 1660 - v/ s -sr (note 5) b 25 - 1135 - v/ s slew rate (v out = 4v p-p , a v = +1, +r s = 620 ? ) +sr b 25 - 1125 - v/ s -sr (note 5) b 25 - 800 - v/ s electrical specifications v supply = 5v, a v = +1, r l = 100 ? , unless otherwise specified (continued) parameter test conditions (note 3) test level temp. ( o c) min typ max units HFA1115
4 application information relevant application notes the following application notes pertain to the HFA1115: ? an9653-use and application of output limiting amplifiers ? an9752-sync stripper and sync inserter for composite video these publications may be obtained from intersil?s web site (http://www.intersil.com) or via our answerfax system. HFA1115 advantages the HFA1115 features a novel design which allows the user to select from three closed loop gains, without any external components. the result is a more flexible product, fewer part types in inventory, and more efficient use of board space. implementing a gain of 2, cable driver with this ic eliminates the two gain setting resistors, which frees up board space for termination resistors. like most newer high performance amplifiers, the HFA1115 is a current feedback amplifier (cfa). cfas offer high bandwidth and slew rate at low supply currents, but can be difficult to use because of their sensitivity to feedback capacitance and parasitics on the inverting input (summing node). the HFA1115 eliminates these concerns by bringing the gain setting resistors on-chip. this yields the optimum placement and value of the feedback resistor, while minimizing feedback and summing node parasitics. because there is no access to the summing node, the pcb parasitics do not impact performance at gains of +2 or -1 (see ?unity gain considerations? for discussion of parasitic impact on unity gain performance). slew rate (v out = 5v p-p , a v = +2) +sr b 25 - 1265 - v/ s -sr (note 5) b 25 - 870 - v/ s settling time (v out = +2v to 0v step, note 4) to 0.1% b 25 - 23 - ns to 0.05% b 25 - 33 - ns to 0.02% b 25 - 45 - ns video characteristics differential gain f = 3.58mhz, a v = +2, r l = 150 ? b25-0.02-% differential phase f = 3.58mhz, a v = +2, r l = 150 ? b 25 - 0.03 - degrees output limiting characteristics a v = +2, v h = +1v, v l = -1v, unless otherwise specified limit accuracy (note 4) v in = 1.6v, a v = -1 a full -125 -70 125 mv overdrive recovery time (note 4) v in = 1v b 25 - 0.8 - ns negative limit range b 25 -5.0 to +2.5 v positive limit range b 25 -2.5 to +5.0 v limit input bias current a full - 85 200 a limit input bandwidth c 25 - 100 - mhz power supply characteristics power supply range c 25 4.5 - 5.5 v power supply current (note 4) a 25 6.6 6.9 7.1 ma afull-7.17.3ma note: 3. test level: a. production tested; b. typical or guaranteed limit based on characterization; c. design typical for information only. 4. see typical performance curves for more information. 5. slew rates are asymmetrical if the output swings below gnd (e.g., a bipolar signal). positive unipolar output signals have sy mmetric positive and negative slew rates comparable to the +sr specification. see the ?application information? section, and the pulse response grap hs for details. electrical specifications v supply = 5v, a v = +1, r l = 100 ? , unless otherwise specified (continued) parameter test conditions (note 3) test level temp. ( o c) min typ max units HFA1115
5 the HFA1115?s closed loop gain implementation provides better gain accuracy, lower offset and output impedance, and better distortion compared with open loop buffers. closed loop gain selection this ?buffer? operates in closed loop gains of -1, +1, or +2, and gain selection is accomplished via connections to the inputs. applying the input signal to +in and floating -in selects a gain of +1 (see next section for layout caveats), while grounding -in selects a gain of +2. a gain of -1 is obtained by applying the input signal to -in with +in grounded through a 50 ? resistor. the table below summarizes these connections: unity gain considerations unity gain selection is accomplished by floating the -input of the HFA1115. anything that tends to short the -input to gnd, such as stray capacitance at high frequencies, will cause the amplifier gain to increase toward a gain of +2. the result is excessive high frequency peaking, and possible instability. even the minimal amount of capacitance associated with attaching the -input lead to the pcb results in approximately 3db of gain peaking. at a minimum this requires due care to ensure the minimum capacitance at the -input connection. . table 1 lists five alternate methods for configuring the HFA1115 as a unity gain buffer, and the corresponding performance. the implementations vary in complexity and involve performance trade-offs. the easiest approach to implement is simply shorting the two input pins together, and applying the input signal to this common node. the amplifier bandwidth drops from 400mhz to 200mhz, but excellent gain flatness is the benefit. another drawback to this approach is that the amplifier input noise voltage and input offset voltage terms see a gain of +2, resulting in higher noise and output offset voltages. alternately, a 100pf capacitor between the inputs shorts them only at high frequencies, which prevents the increased output offset voltage but delivers less gain flatness. another straightforward approach is to add a 620 ? resistor in series with the positive input. this resistor and the HFA1115 input capacitance form a low pass filter which rolls off the signal bandwidth before gain peaking occurs. this configuration was employed to obtain the datasheet ac and transient parameters for a gain of +1. non-inverting input source impedance for best operation, the dc source impedance seen by the non-inverting input should be 50 ?. this is especially important in inverting gain configurations where the non- inverting input would normally be connected directly to gnd. pulse undershoot and asymmetrical slew rates the HFA1115 utilizes a quasi-complementary output stage to achieve high output current while minimizing quiescent supply current. in this approach, a composite device replaces the traditional pnp pulldown transistor. the composite device switches modes after crossing 0v, resulting in added distortion for signals swinging below ground, and an increased undershoot on the negative portion of the output waveform (see figures 9, 13, and 17). this undershoot isn?t present for small bipolar signals, or large positive signals. another artifact of the composite device is asymmetrical slew rates for output signals with a negative voltage component. the slew rate degrades as the output signal crosses through 0v (see figures 9, 13, and 17), resulting in a slower overall negative slew rate. positive only signals have symmetrical slew rates as illustrated in the large signal positive pulse response graphs (see figures 7, 11, and 15). pc board layout this amplifier?s frequency response depends greatly on the care taken in designing the pc board. the use of low inductance components such as chip resistors and chip capacitors is strongly recommended, while a solid ground plane is a must! attention should be given to decoupling the power supplies. a large value (10 f) tantalum in parallel with a small value (0.1 f) chip capacitor works well in most cases. terminated microstrip signal lines are recommended at the input and output of the device. capacitance directly on the output must be minimized, or isolated as discussed in the next section. for unity gain applications, care must also be taken to minimize the capacitance to ground at the amplifier?s inverting input. at higher frequencies this capacitance tends to short the -input to gnd, resulting in a closed loop gain which increases with frequency. this causes excessive high frequency peaking and potentially other problems as well. an example of a good high frequency layout is the evaluation board shown in figure 2. gain (a v ) connections +input (pin 3) -input (pin 2) -1 50 ? to gnd input +1 input nc (floating) +2 input gnd table 1. unity gain performance for various implementations approach peak- ing (db) bw (mhz) +sr/-sr (v/ s) 0.1db gain flatness (mhz) remove pin 2 2.5 400 1200/850 20 +r s = 620 ? 0.6 170 1125/800 25 +r s = 620 ? and remove pin 2 0 165 1050/775 65 short pins 2, 3 0 200 875/550 45 100pf cap. be- tween pins 2, 3 0.2 190 900/550 19 HFA1115
6 driving capacitive loads capacitive loads, such as an a/d input, or an improperly terminated transmission line degrade the amplifier?s phase margin resulting in frequency response peaking and possible oscillations. in most cases, the oscillation can be avoided by placing a resistor (r s ) in series with the output prior to the capacitance. figure 1 details starting points for the selection of this resistor. the points on the curve indicate the r s and c l combinations for the optimum bandwidth, stability, and settling time, but experimental fine tuning is recommended. picking a point above or to the right of the curve yields an overdamped response, while points below or left of the curve indicate areas of underdamped performance. r s and c l form a low pass network at the output, thus limiting system bandwidth well below the amplifier bandwidth of 200mhz (a v = +1). by decreasing r s as c l increases (as illustrated by the curves), the maximum bandwidth is obtained without sacrificing stability. in spite of this, bandwidth still decreases as the load capacitance increases. for example, at a v = +1, r s = 50 ? , c l = 22pf, the overall bandwidth is 185mhz, but the bandwidth drops to 50mhz at a v =+1, r s = 15 ? , c l = 330pf. evaluation board the performance of the HFA1115 may be evaluated using the hfa11xx evaluation board, slightly modified as follows: 1. 1. remove the 510 ? feedback resistor (r 2 ), and leave the connection open. 2. 2. a. for a v = +1 evaluation, remove the 510 ? gain set- ting resistor (r 1 ), and leave pin 2 floating. b. for a v = +2, replace the 510 ? gain setting resistor with a 0 ? resistor to gnd. the layout and modified schematic of the board are shown in figure 2. to order evaluation boards (part number hfa11xxeval), please contact your local sales office. limiting operation general the HFA1115 features user programmable output clamps to limit output voltage excursions. limiting action is obtained by applying voltages to the v h and v l terminals (pins 8 and 5) of the amplifier. v h sets the upper output limit, while v l sets the lower limit level. if the amplifier tries to drive the output above v h , or below v l , the clamp circuitry limits the output voltage at v h or v l ( the limit accuracy), respectively. the low input bias currents of the limit pins allow them to be driven by simple resistive divider circuits, or active elements such as amplifiers or dacs. limit circuitry figure 3 shows a simplified schematic of the HFA1115 input stage, and the high limit (v h ) circuitry. as with all current feedback amplifiers, there is a unity gain buffer (q x1 - q x2 ) between the positive and negative inputs. this buffer forces -in to track +in, and sets up a slewing current of: i slew = (v -in - v out )/r f + v -in /r g r s ( ? ) load capacitance (pf) 50 45 40 35 30 25 20 15 10 5 0 0 40 80 120 160 200 240 280 320 360 400 figure 1. recommended series resistor vs load capacitance a v = +1 a v = +2 board schematic (modified) top layout bottom layout figure 2. evaluation board schematic (after modification for buffer use) and layout 1 2 3 4 8 7 6 5 +5v 10 f 0.1 f v h 50 ? gnd gnd -5v 0.1 f 10 f 50 ? in out v l r 1 = (a v = +1) or 0 ? (a v = +2) r 1 v h +in v l v+ gnd 1 v- out HFA1115
7 this current is mirrored onto the high impedance node (z) by q x3 -q x4 , where it is converted to a voltage and fed to the output via another unity gain buffer. if no limiting is utilized, the high impedance node may swing within the limits defined by q p4 and q n4 . note that when the output reaches its quiescent value, the current flowing through -in is reduced to only that small current (-i bias ) required to keep the output at the final voltage. tracing the path from v h to z illustrates the effect of the limit voltage on the high impedance node. v h decreases by 2v be (q n6 and q p6 ) to set up the base voltage on q p5 . q p5 begins to conduct whenever the high impedance node reaches a voltage equal to q p5 ?s base voltage + 2v be (q p5 and q n5 ). thus, q p5 limits node z whenever z reaches v h . r 1 provides a pull-up network to ensure functionality with the limit inputs floating. a similar description applies to the symmetrical low limit circuitry controlled by v l . when the output is limited, the negative input continues to source a slewing current (i limit ) in an attempt to force the output to the quiescent voltage defined by the input. q p5 must sink this current while limiting, because the -in current is always mirrored onto the high impedance node. the limiting current is calculated as: i limit = (v -in - v out limited )/r f + v -in /r g . as an example, a unity gain circuit with v in = 2v, and v h =1v, would have i limit = (2v - 1v)/350 ? +2v/ = 2.8ma (r g = because -in is floated for unity gain applications). note that i cc increases by i limit when the output is limited. limit accuracy the limited output voltage will not be exactly equal to the voltage applied to v h or v l . offset errors, mostly due to v be mismatches, necessitate a limit accuracy parameter which is found in the device specifications. limit accuracy is a function of the limiting conditions. referring again to figure 3, it can be seen that one component of limit accuracy is the v be mismatch between the q x6 transistors, and the q x5 transistors. if the transistors always ran at the same current level there would be no v be mismatch, and no contribution to the inaccuracy. the q x6 transistors are biased at a constant current, but as described earlier, the current through q x5 is equivalent to i limit . v be increases as i limit increases, causing the limited output voltage to increase as well. i limit is a function of the overdrive level ((a v x v in - v limit ) / v limit ), so limit accuracy degrades as the overdrive increases (see figures 28 and 29). for example, accuracy degrades from -20mv to +30mv when the overdrive increases from 100% to 200% (a v = +2, v h =500mv ). consideration must also be given to the fact that the limit voltages have an effect on amplifier linearity. the ?linearity near limit voltage? curves, figures 30 and 31, illustrate the impact of several limit levels on linearity. limit range unlike some competitor devices, both v h and v l have usable ranges that cross 0v. while v h must be more positive than v l , both may be positive or negative, within the range restrictions indicated in the specifications. for example, the HFA1115 could be limited to ecl output levels by setting v h = -0.8v and v l = -1.8v. v h and v l may be connected to the same voltage (gnd for instance) but the result won?t be a dc output voltage from an ac input signal. a 150mv - 200mv ac signal will still be present at the output. recovery from overdrive the output voltage remains at the limit level as long as the overdrive condition remains. when the input voltage drops below the overdrive level (v limit /a v ) the amplifier returns to linear operation. a time delay, known as the overdrive recovery time, is required for this resumption of linear operation. overdrive recovery time is defined as the difference between the amplifier?s propagation delay exiting limiting and the amplifier?s normal propagation delay, and it is a strong function of the overdrive level. figure 32 details the overdrive recovery time for various limit and overdrive levels benefits of output limiting the plots of ?pulse response without limiting? and ?pulse response with limiting? (figures 4 and 5) highlight the advantages of output limiting. besides the obvious benefit of constraining the output swing to a defined range, limiting the output excursions also keeps the output transistors from saturating, which prevents unwanted saturation artifacts from distorting the output signal. output limiting also takes advantage of the HFA1115?s ultra-fast overdrive recovery +1 +in v- v+ q p1 q n1 v- q n3 q p3 q p4 q n2 q p2 q n4 q p5 q n5 z v+ -in v out i limit q p6 q n6 v h r 1 v -in 200 ? figure 3. HFA1115 simplified v h limit circuitry 50k ? r f = 350 ? (internal) r g = 350 ? (internal) HFA1115
8 time, reducing the recovery time from 2.5ns to 0.5ns, based on the amplifier?s normal propagation delay of 1.2ns. typical performance curves v supply = 5v, t a = 25 o c, r l = 100 ? , unless otherwise specified figure 4. pulse response without limiting figure 5. pulse response with limiting figure 6. small signal positive pulse response figure 7. large signal positive pulse response time (5ns/div.) input voltage (v) a v = +2 0 out -0.5 -1.0 0.5 1.0 1.5 2.0 output voltage (v) 0 -1.0 -2.0 1.0 2.0 3.0 4.0 in time (5ns/div.) input voltage (v) 0 out 0.5 1.0 -0.5 in output voltage (v) 0 1.0 2.0 -1.0 -1.0 1.5 2.0 a v = +2 v h = +2.0v, v l = 0v 200 150 100 50 0 -50 -100 output voltage (mv) time (5ns/div.) 250 300 a v = +2 2.0 1.5 1.0 0.5 0 -0.5 -1.0 output voltage (v) 2.5 3.0 time (5ns/div.) a v = +2 HFA1115
9 figure 8. small signal bipolar pulse response figure 9. large signal bipolar pulse response figure 10. small signal positive pulse response figure 11. large signal positive pulse response figure 12. small signal bipolar pulse response figure 13. large signal bipolar pulse response typical performance curves v supply = 5v, t a = 25 o c, r l = 100 ? , unless otherwise specified (continued) 200 150 100 50 0 -50 -100 -150 -200 output voltage (mv) time (5ns/div.) a v = +2 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 output voltage (v) time (5ns/div.) a v = +2 a v = +1 200 150 100 50 0 -50 -100 output voltage (mv) 250 300 time (5ns/div.) a v = +1 2.0 1.5 1.0 0.5 -0.5 -1.0 output voltage (v) 2.5 3.0 0 time (5ns/div.) a v = +1 200 150 100 50 0 -50 -100 -150 -200 output voltage (mv) time (5ns/div.) a v = +1 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 output voltage (v) time (5ns/div.) HFA1115
10 figure 14. small signal positive pulse response figure 15. large signal positive pulse response figure 16. small signal bipolar pulse response figure 17. large signal bipolar pulse response figure 18. frequency response figure 19. frequency response for various output voltages typical performance curves v supply = 5v, t a = 25 o c, r l = 100 ? , unless otherwise specified (continued) a v = -1 200 150 100 50 0 -50 -100 output voltage (mv) 250 300 time (5ns/div.) a v = -1 2.0 1.5 1.0 0.5 0 -0.5 -1.0 output voltage (v) 2.5 3.0 time (5ns/div.) a v = -1 200 150 100 50 0 -50 -100 -150 -200 output voltage (mv) time (5ns/div.) a v = -1 2.0 1.5 0.5 0 -0.5 -1.0 -1.5 -2.0 output voltage (v) 1.0 time (5ns/div.) frequency (mhz) normalized phase (degrees) normalized gain (db) 1 10 100 1000 3 0 -3 -6 0 90 180 270 360 a v = +1 a v = +2 v out = 200mv p-p gain phase a v = -1 a v = -1 a v = +1 a v = +2 frequency (mhz) normalized gain (db) phase (degrees) 1 10 100 1000 3 0 -3 -6 0 90 180 270 360 a v = +2 v out = 1v p-p v out = 2.5v p-p v out = 4v p-p v out = 1v p-p v out = 2.5v p-p gain phase v out = 4v p-p HFA1115
11 figure 20. frequency response for various output voltages figure 21. frequency response for various output voltages figure 22. full power bandwidth figure 23. -3db bandwidth vs temperature figure 24. gain flatness figure 25. reverse isolation (s 12 ) typical performance curves v supply = 5v, t a = 25 o c, r l = 100 ? , unless otherwise specified (continued) frequency (mhz) phase (degrees) gain (db) 1 10 100 1000 3 0 -3 -6 0 90 180 270 360 a v = +1 v out = 1v p-p v out = 1v p-p v out = 4v p-p v out = 2.5v p-p gain phase v out = 4v p-p v out = 2.5v p-p frequency (mhz) normalized phase (degrees) gain (db) 1 10 100 1000 3 0 -3 -6 0 90 180 270 360 a v = -1 v out = 4v p-p v out = 2.5v p-p v out = 1v p-p gain phase v out = 4v p-p v out = 2.5v p-p v out = 1v p-p frequency (mhz) normalized gain (db) 1 10 100 1000 3 0 -3 -6 -9 a v = +1, v out = 4v p-p a v = -1, v out = 5v p-p a v = +2, v out = 5v p-p -75 -50 0 50 100 125 170 180 190 200 210 220 230 240 250 260 temperature ( o c) bandwidth (mhz) -25 25 75 a v = +2 a v = -1 a v = +1 frequency (mhz) normalized gain (db) 1 10 100 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 a v = +1 v out = 200mv p-p a v = +2 a v = -1 frequency (mhz) gain (db) 1 10 100 1000 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 a v = +2 a v = +1 a v = -1 HFA1115
12 figure 26. output resistance figure 27. settling time response figure 28. v h limit accuracy vs overdrive figure 29. v l limit accuracy vs overdrive figure 30. linearity near limit voltage figure 31. linearity near limit voltage typical performance curves v supply = 5v, t a = 25 o c, r l = 100 ? , unless otherwise specified (continued) 1k 100 10 1 0.1 0.01 0.3 1 10 100 frequency (mhz) 1000 output resistance ( ? ) a v = +2 3 13233343 53 6373 83 93103 0.1 0.05 0 -0.025 -0.05 -0.1 0.025 settling error (%) time (ns) overdrive (% of v h ) limit accuracy (mv) a v = +2 0 100 200 300 400 500 -150 -100 -50 0 50 100 150 v h = +2.0v v h = +500mv v h = +1v overdrive (% of v l ) limit accuracy (mv) a v = +2 0 100 200 300 400 500 -150 -100 -50 0 50 100 150 v l = -2.0v v l = -500mv v l = -1.0v -2.0 -1.0 0 1.0 2.0 0 1.0 2.0 a v x v in (v) linearity error (%) 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 -1.5 -0.5 0.5 1.5 a v = +2 v l = -500mv v h = +1v v h = +2v v l = -2v v l = -1v v h = +500mv -2.0 -1.0 0 1.0 2.0 0 1.0 2.0 a v x v in (v) linearity error (%) -1.5 1.5 1.2 1.4 1.6 1.8 0.2 0.4 0.6 0.8 -0.5 0.5 a v = +1 v h = +1v v h = +2v v l = -2v v l = -1v v l = -500mv v h = +500mv HFA1115
13 figure 32. overdrive recovery time vs overdrive figure 33. output voltage vs temperature figure 34. supply current vs supply voltage figure 35. rise and fall times vs temperature figure 36. input noise characteristics typical performance curves v supply = 5v, t a = 25 o c, r l = 100 ? , unless otherwise specified (continued) 100 200 300 400 0 0.5 1.0 1.5 2.0 2.5 overdrive (% of v h or v l ) overdrive recovery time (ns) 0 a v = +2 v h = +2v v h = +3v v l = -3v v l = -2v v l = -1v v h = +1v 3.0 3.5 4.0 3.6 3.5 3.4 3.3 3.2 3.1 2.9 2.8 2.7 2.6 -50 -25 0 25 50 75 100 125 temperature ( o c) output voltage (v) 3.0 +v out (r l = 50 ? ) |-v out | (r l = 50 ? ) +v out (r l = 100 ? ) |-v out | (r l = 100 ? ) a v = -1 supply voltage ( v) supply current (ma) 4.0 4.5 5.0 5.5 6.0 6.5 7.0 6.7 6.8 6.9 7.0 7.1 -75 -50 0 50 100 125 1.6 1.7 1.8 1.9 2.0 2.1 2.2 temperature ( o c) rise/fall times (ns) -25 25 75 rise times a v = -1 a v = +1 a v = -1 fall times a v = +2 a v = +2 v out = 500mv p-p a v = +2 a v = +1 100 10 1 0.1 1 10 100 100 10 1 frequency (khz) noise voltage (nv/ hz) noise current (pa/ hz) e ni i ni HFA1115
14 all intersil u.s. products are manufactured, assembled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com die characteristics die dimensions: 59 mils x 58.2 mils x 19 mils 1500 m x 1480 m x 483 m metallization: type: metal 1: aicu(2%)/tiw thickness: metal 1: 8k ? 0.4k ? type: metal 2: aicu(2%) thickness: metal 2: 16k ? 0.8k ? substrate potential (powered up): floating (recommend connection to v-) passivation: type: nitride thickness: 4k ? 0.5k ? transistor count: 89 metallization mask layout HFA1115 v- out +in -in v+ v l v h HFA1115

▲Up To Search▲

Price & Availability of HFA1115

	To Download HFA1115 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .